The present invention relates generally to imaging devices. More particularly, the invention is directed to an integrated imaging device having a charge-coupled device (CCD) imager array, an image processing unit, and on-chip charge drains and storage registers that provide exposure control of the image data, field interlacing, pseudo interlacing or non-interlacing capabilities, and video compression.
Imaging devices are useful for electronically reproducing a field of view. Once the image is converted into an electrical signal, the image can be enhanced or altered using various forms of signal processing such as spatial filtering, noise suppression, and video compression. Normally, signal processing is controlled by discrete circuitry or software after collecting and passing image data into and then from the imaging device. Select CCD imagers allow for limited, on-chip signal processing capabilities such as spatial filtering or image interlacing.
Generally, transferring an image from the imaging array is through a transfer register. The transfer register is approximately the same width as a row of the imaging array. A group of vertical registers are used to transfer an image, one row at a time, from the imaging array into the transfer register. A charge dump drain removes or dumps unwanted data during this transfer. Using the dump drain to remove image lines one frame of data, while retaining others (window). This is one method for data reduction for the image. This data reduction is useful in an application such as tracking a moving object in the image.
The addition of the dump drain provides for quicker spatial filtering processing than previously possible since the dump drain performs the processing simultaneously with the image transferring operation. This increases the overall image processing speed and reduces the need for additional circuitry to perform the specific signal processing function. However, the addition of the dump drain provides only limited signal processing or data manipulation capabilities. Other processing functions that do not require or use the dump drain still limit the speed of the imaging system. This causes additional problems such as delay, or requires additional discrete processing circuitry that is expensive. Also, the transfer register is limited in what types of processing can be done since usually only a single channel is provided.
A temporary storage register, generally of the same size as the imaging array, may be added to an imaging device to perform image interlacing. A first field image of alternating rows or columns stored in the storage register is combined with a second field image having alternating rows or columns lacking in the first field image. The resulting field is an interlaced image having a higher resolution than either the first or second field image alone. Yet, most imaging arrays are limited to doing only one or two signal processing or image manipulation functions such as image interlacing, non-interlacing, windowing or other type functions.
From the above, it is seen that an improved imaging device and an associated charge transfer apparatus is desired that is capable of performing a variety of signal processing and image manipulation functions, such as image compression, Fourier transform, spatial filtering among others.